Gate electrode with a shrink spacer

A method of forming a semiconductor device, comprising:

• forming a dielectric material layer on a semiconductor layer;
• forming a gate electrode material layer on said dielectric material layer;
• forming mask features on said gate electrode material layer, wherein forming said mask features includes performing a first lithography process so as to define a gate length and performing a second lithography process so as to define a preliminary lateral distance between said gate electrode structures, said first lithography process including:
• forming a mask layer on said gate electrode material layer;
• forming a first resist layer on said mask layer and patterning said first resist layer;
• forming a patterned mask layer based on said patterned first resist layer;
• forming a second resist layer on said patterned mask layer and patterning said second resist layer;
• and
• etching said patterned mask layer based on said patterned second resist layer to obtain said mask features;
• forming a spacer layer on said mask features and at sidewalls of said mask features and on said gate electrode material layer between said mask features;
• removing a portion of said spacer layer from said gate electrode material layer between said mask features to define spacers on said gate electrode material between said mask features, and
• etching said gate electrode material layer and said dielectric material layer using said mask features and said spacers as an etch mask to obtain gate electrode structures.