Double Sided NMOS/PMOS Structure and Methods of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJam-Wem Lee
Life of this patent
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Abstract
A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
Claims20
An integrated circuit structure comprising:
- a first chip comprising:
- a dielectric layer comprising a top surface and a bottom surface;
- a first semiconductor layer overlying and bonded to the top surface of the dielectric layer;
- a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type, wherein the first MOS transistor comprises:
- a first gate dielectric overlying and contacting the first semiconductor layer;
- and
- a first gate electrode overlying the first gate dielectric;
- a second semiconductor layer underlying and bonded to the bottom surface of the dielectric layer;
- and
- a second MOS transistor of a second conductivity type opposite to the first conductivity type, wherein the second MOS transistor comprises:
- a second gate dielectric underlying and contacting the second semiconductor layer;
- and
- a second gate electrode underlying the second gate dielectric.
An integrated circuit structure comprising:
- an oxide layer comprising a top surface and a bottom surface;
- a first silicon layer overlying and bonded to the oxide layer, wherein the first silicon layer has a (100) surface orientation;
- an n-type Metal Oxide-Semiconductor (NMOS) transistor comprising:
- a first gate dielectric overlying the first silicon layer;
- a first gate electrode overlying the first gate dielectric;
- and
- a first source/drain region in the first silicon layer;
- a second silicon layer underlying and bonded to the oxide layer, wherein the second silicon layer has a (110) surface orientation;
- a p-type Metal Oxide-Semiconductor (PMOS) transistor comprising:
- a second gate dielectric underlying the second silicon layer;
- a second gate electrode underlying the second gate dielectric;
- and
- a second source/drain region in the second silicon layer;
- and
- a through-via penetrating through the oxide layer, the first silicon layer, and the second silicon layer.
A method comprising:
- forming a first transistor at a top surface of a Semiconductor-On-Insulator (SOI) substrate, wherein the SOI substrate comprises:
- a first semiconductor layer;
- a dielectric layer over and bonded to the first semiconductor layer;
- and
- a second semiconductor layer over and bonded to the dielectric layer, wherein the first transistor is formed on the second semiconductor layer;
- thinning the first semiconductor layer;
- forming a second transistor on the first semiconductor layer, wherein the first transistor and the second transistor are of opposite conductivity types;
- and
- forming a through-via penetrating through the first semiconductor layer, the dielectric layer, and the second semiconductor layer.
Dependencies are inferred from the claim text.