3d semiconductor device and 3d logic array structure thereof
AssigneeMacronix International Co., Ltd.
InventorShih-Hung Chen
Life of this patent
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Abstract
A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.
Claims20
A 3D semiconductor device, comprising:
- an array structure, having Y first contacts located at a first side of the array structure, wherein Y is within MN-1 to MN, Y, M and N are natural numbers, and M is larger or equal to 2;
- a first periphery line structure;
- and
- a first 3D logic array structure, including:
- N sets of first gate electrodes, wherein each set of the first gate electrodes has M first gate electrodes;
- a first input electrode;
- and
- Y first output electrodes;
- wherein the Y first output electrodes connect the Y first contacts, the M·N first gate electrodes and the first input electrode connect the first periphery line structure.
A 3D logic array structure, comprising:
- N sets of gate electrodes, wherein each set of the gate electrodes has M gate electrodes;
- an input electrode;
- and
- Y output electrodes, wherein the Y output electrodes connect Y contacts of an array structure, the Y contacts are located at a side of the array structure, the M·N gate electrodes and the input electrode connect a periphery line structure, Y is within MN-1 to MN, Y, M and N are natural numbers, and M is larger or equal to 2.
A 3D logic array structure, comprising:
- M first gate electrodes, each first gate electrode being applied a positive voltage, a negative voltage or a ground voltage;
- a plurality of first gates, each first gate being connected to one of the first gate electrodes in turn;
- N second gate electrodes, each second gate electrode being applied the positive voltage, the negative voltage or the ground voltage;
- a plurality of second gates, each second gate being connected to one of the second gate electrodes in turn;
- and
- Y semiconductor stacks, each semiconductor stack being located between two of the first gates and two of the second gates;
- wherein the number of the first gates is equal to that of the second gates, the number of the first gates is equal to or smaller than M*N+1, Y is equal to or smaller than M*N, M and N are natural numbers, M and N are larger or equal to 4, and the greatest common divisor of M and N is 1.
Dependencies are inferred from the claim text.