Vertical transistor devices for embedded memory and logic technologies

A vertical transistor device, comprising:

• an epitaxial source semiconductor region disposed on a substrate;
• an epitaxial channel semiconductor region disposed on the source semiconductor region;
• an epitaxial drain semiconductor region disposed on the channel semiconductor region;
• and
• a gate electrode region surrounding a plurality of sidewalls of the semiconductor channel region, wherein a composition of the gate electrode region varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

A method of fabricating a vertical transistor device having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the method comprising:

• depositing a source semiconductor region on the crystalline substrate;
• depositing growing a channel semiconductor region on the source semiconductor region;
• depositing a drain semiconductor region on the channel semiconductor region;
• etching through the drain, channel, and source semiconductor regions to form a plurality of sidewalls through the drain, channel, and source semiconductor regions;
• and
• forming a gate dielectric region and a gate electrode on a plurality of channel semiconductor region sidewalls, wherein the depositing further comprises modifying growth conditions to vary the semiconductor composition across a thickness of the channel semiconductor region.

A computing device, comprising:

• memory to store electronic data;
• and
• a processor coupled to the memory, the processor to process electronic data, the processor includes an integrated circuit die having a plurality of vertical transistor devices, at least one vertical transistor device comprising:
• a first epitaxial semiconductor region disposed on a substrate;
• a second epitaxial semiconductor region disposed on the first semiconductor region;
• a third epitaxial semiconductor region disposed on the second semiconductor region;
• and
• a gate electrode region surrounding a plurality of sidewalls of the second semiconductor region, wherein a composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.