Semiconductor structure and device and methods of forming same using selective epitaxial process
AssigneeASM IP Holding B.V.
InventorsQi Xie, Vladimir Machkaoutsan, Jan Willem Maes
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Abstract
Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.
Claims20
A method of forming a semiconductor structure, the method comprising the steps of:
- providing a substrate comprising silicon;
- forming a buffer layer comprising Si1-xGex, where x ranges from 0 to about 0.8, overlying the substrate;
- using a first selective epitaxial process, forming a first feature comprising silicon overlying the buffer layer on a surface;
- and
- using a second selective epitaxial process, forming a second feature comprising Si1-yGey, where y ranges from about 0.1 to 1, on the surface.
A semiconductor structure comprising:
- a substrate comprising silicon;
- a buffer layer comprising Si1-xGex, where x ranges from 0 to about 0.5, overlying the substrate;
- a p well region formed within the buffer layer;
- an n well region formed within the buffer layer;
- one or more fin structures formed using the p well region and a layer comprising silicon;
- one or more fin structures formed using the n well region and a layer comprising Si1-yGey, where y ranges from about 0.1 to 1;
- and
- an insulating layer formed overlying a portion of the buffer layer.
A CMOS device comprising:
- a substrate comprising silicon;
- a buffer layer comprising Si1-xGex, where x ranges from 0 to about 0.5, overlying the substrate;
- a p well region formed within the buffer layer;
- an n well region formed within the buffer layer;
- one or more fin structures formed using the p well region and a layer comprising silicon;
- one or more fin structures formed using the n well region and a layer comprising Si1-yGey, where y ranges from about 0.1 to 1;
- and
- an insulating layer formed overlying a portion of the buffer layer.
The CMOS device 17, wherein the insulating layer is formed using H2Si[N(C2H5)2]2 and an O2 plasma.
Dependencies are inferred from the claim text.