SCRs with Checker Board Layouts

An Electro Static Discharge (ESD) protection circuit comprising:

• a semiconductor substrate of a first conductivity type;
• a first well region and a second well region of a second conductivity type opposite to the first conductivity type, wherein the first well region and the second well region are separated from each other by a portion of the semiconductor substrate;
• a first semiconductor strip extending in a row direction and overlapping and contacting the first well region, wherein the first semiconductor strip comprises:
• a first heavily doped portion of the first conductivity type;
• a second heavily doped portion of the second conductivity type;
• and
• a third portion of the second conductivity type connecting the first portion to the second portion;
• a first gate stack overlapping the third portion of the first semiconductor strip;
• and
• a second semiconductor strip extending in the row direction and overlapping and contacting the second well region, wherein the second semiconductor strip comprises:
• a fourth heavily doped portion of the first conductivity type;
• a fifth heavily doped portion of the second conductivity type;
• and
• a sixth portion of the second conductivity type connecting the fourth portion to the fifth portion, wherein the first and the fifth portions are in a same first column, and wherein the second and the fourth portions are in a same second column;
• a second gate stack overlapping the sixth portion of the second semiconductor strip;
• and
• a first conductor electrically connecting the second portion to the fourth portion, wherein the first and the second gate stacks and the first and the second semiconductor strips are comprised in a first Silicon-Controlled Rectifier (SCR)/diode-string unit.

An Electro-Static Discharge (ESD) protection circuit comprising:

• a p-type semiconductor substrate;
• a diode string comprising a first, a second, a third, and a fourth diode, wherein the first, the second, the third, and the fourth diodes are aligned sequentially in a column, and wherein each of the first, the second, the third, and the fourth diodes comprises:
• a p+ semiconductor strip as an anode;
• an n-type semiconductor strip and a n+ semiconductor strip as a cathode, wherein the anodes and the cathodes of the first, the second, the third, and the fourth diodes form an array, and wherein in each of rows and columns of the array, the anodes and the cathodes are allocated in an alternating layout;
• and
• a gate electrode overlapping the n-type semiconductor strip;
• and
• four n-well regions, each overlapped by and in contact with one of the first, the second, the third, and the fourth diodes, wherein the four n-well regions are separated from each other by portions of the p-type semiconductor substrate.