Semiconductor Device and Method for Forming a Semiconductor Device

A semiconductor device comprising an insulated gate bipolar transistor arrangement, the insulated gate bipolar transistor arrangement comprising a plurality of configuration regions arranged within a cell region of the semiconductor device at a main surface of the semiconductor substrate of the semiconductor device, wherein each configuration region of the plurality of configuration regions comprises emitter-side insulated gate bipolar transistor structures,

• wherein the insulated gate bipolar transistor arrangement comprises a collector layer and a drift layer, wherein the collector layer is arranged at a backside surface of the semiconductor substrate of the semiconductor device and the drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the plurality of configuration regions,
• wherein the collector layer comprises a plurality of doping regions within the cell region at the backside surface of the semiconductor substrate of the semiconductor device, wherein the doping regions of the plurality of doping regions comprise at least partly different charge carrier life times, different conductivity types or different doping concentrations,
• wherein the configuration regions of the plurality of configuration regions and the doping regions of the plurality of doping regions are configured so that the average densities of free charge carriers within parts of the drift layer facing the respective doping regions of the plurality of doping regions differ from each other by less than 20% of an average densities of free charge carriers within the cell region in an on-state of the semiconductor device.

A method for forming a semiconductor device comprising an insulated gate bipolar transistor arrangement, the method comprising:

• forming at least a first configuration region of emitter-side insulated gate bipolar transistor structures of the insulated gate bipolar transistor arrangement and a second configuration region of emitter-side insulated gate bipolar transistor structures of the insulated gate bipolar transistor arrangement arranged at a main surface of a semiconductor substrate of the semiconductor device;
• and
• forming a collector layer of the insulated gate bipolar transistor arrangement arranged at a backside surface of the semiconductor substrate of the semiconductor device, wherein a drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region,
• wherein the collector layer comprises at least a first doping region laterally adjacent to a second doping region, wherein the first doping region and the second doping region comprise different charge carrier life times, different conductivity types or different doping concentrations,
• wherein the first configuration region is located with at least a partial lateral overlap to the first doping region and the second configuration region is located with at least a partial lateral overlap to the second doping region,
• wherein the first configuration region, the first doping region, the second configuration region and the second doping region are configured so that a first average density of free charge carriers within a part of the drift layer facing the first doping region differs from a second average density of free charge carriers within a part of the drift layer facing the second doping region by less than 20% of the second average density of free charge carriers in an on-state of the semiconductor device.