Concurrent optimization of timing, area, and leakage power
AssigneeSynopsys, Inc.
InventorsYiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
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Abstract
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.
Claims18
In an electronic design automation (EDA) tool, a method for performing circuit synthesis, the method comprising:
- receiving a cell for optimization;
- determining timing criticality of the cell;
- determining, by a processor, timing criticality of a driver cell that drives an input of the cell;
- and
- in response to determining that the cell is timing critical, optimizing the cell for timing, but not for area or power leakage.
A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for performing circuit synthesis, the method comprising:
- receiving a cell for optimization;
- determining timing criticality of the cell;
- determining timing criticality of a driver cell that drives an input of the cell;
- and
- in response to determining that the cell is timing critical, optimizing the cell for timing, but not for area or power leakage.
An apparatus for performing circuit synthesis, comprising:
- a processor;
- and
- a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the computer to perform a method for performing circuit synthesis, the method comprising:
- receiving a cell for optimization;
- determining timing criticality of the cell;
- determining timing criticality of a driver cell that drives an input of the cell;
- and
- in response to determining that the cell is timing critical, optimizing the cell for timing, but not for area or power leakage.
Dependencies are inferred from the claim text.