Circuit arrangement and method for realizing check bit compacting for cross parity codes
AssigneeInfineon Technologies AG
InventorsSven Hosp, Michael Goessel, Klaus Oberlaender
Life of this patent
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Abstract
A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.
Claims20
A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk, wherein the circuit arrangement comprises:
- a first subcircuit having k binary inputs for inputting the k data bits (u=u1, . . . , uk) and M binary outputs for outputting M binary intermediate values (z1=z1(u1, . . . , uk), . . . , zM=zM(u1, . . . , uk)) determined from the data bits, and
- a second subcircuit for transforming the intermediate values (z1, . . . , zM) into the check bits c1, . . . , cm, where m<M and M<k,
- wherein the first subcircuit is configured to determine the intermediate values from the data bits such that there is an association between a determined pair of intermediate values (z1,lj,z2,mj) for each data bit uj that is to be corrected, such that a change in the pair (z1,lj,z2,mj to z1,lj, z2,mj) when only one data bit from the data bits {u1, . . . , uk} has changed to its negated value indicates that the j-th data bit uj has changed to ūj,
- wherein the second subcircuit is configured to transform the intermediate values into check bits such that the check bits associated with the intermediate values determined from the data bits u1, . . . , uk and the check bits associated with the intermediate values determined from the data bits inverted in a respective bit from the data bits that are to be corrected are pairwise different, where m<M.
A decoder for determining a subset of data bits that are to be corrected on the basis of m check bits c1, . . . , cm, wherein the m check bits c1, . . . , cm are formed by a circuit arrangement for determining the check bits c1, . . . , cm for k data bits u1, . . . , uk as claimed in one of the preceding claims, wherein the decoder comprises:
- a third subcircuit for forming a subset of differences Δc1=c1⊕c1′, . . . , Δcm=cm⊕cm′ for the correct check bits c1, . . . , cm and the possibly erroneous check bits c1′, . . . , cm′, these differences being determined from possibly erroneous data bits u1′, . . . , uk′ and possibly erroneous check bits c1′, . . . , cm′,
- a fourth subcircuit for forming a subset of differences Δz1=z1⊕z1′, . . . , ΔzM=zM⊕zM′ from error-free intermediate values z1, . . . , zM and possibly erroneous intermediate values z1′, . . . , zM′, the differences Δz1, . . . , ΔzM being determined from the differences in the intermediate values Δc1, . . . , Δcm, and
- a fifth subcircuit for determining a corrected data bit ujcor having at least three binary inputs for inputting a possibly erroneous data bit u′j and for inputting two differences Δz1,lj,Δz2,rj from intermediate values and a binary output for outputting the corrected data bit ujcor, wherein z1,lj belongs to a first group of intermediate values and z2,rj belongs to a second group of intermediate values, so that when uj changes to uj and also no error occurs, z1,lj changes to z1,lj and z2,rj changes to z2,rj, and the fifth subcircuit is designed such that it outputs ujcor=uj⊕1 when Δz1,lj=Δz2,rj=1.
A method for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk, wherein the method comprises:
- determination of M intermediate values from the k data bits, so that there is an association between a determined pair of intermediate values (z1,lj,z2,mj) for each data bit uj that is to be corrected, so that a change in the pair (z1,lj, z2,mj to z1,lj, z2,mj) when only one data bit from the data bits {u1, . . . , uk} has changed to its negated value indicates that the j-th data bit uj has changed to ūj, and
- transformation of the intermediate values (z1, . . . , zM) into the check bits c1, . . . , cm, wherein the intermediate values are transformed into check bits such that the check bits associated with the intermediate values determined from the data bits u1, . . . , ui, . . . , uk and the check bits associated with the intermediate values determined from the data bits inverted in a respective bit from the data bits that are to be corrected differ in pairs, where m<M and M<k.
Dependencies are inferred from the claim text.