# US 2015/0089329 A1 · Electronic circuit for fitting a virtual address range to a physical memory containing faulty address

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- Number: US 2015/0089329 A1
- Document ID: US20150089329A1
- Status: Published application
- Kind: A1
- Application number: 14/037,487
- Filed: 2013-09-26
- Published: 2015-03-26
- Earliest claimed: 2013-09-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: John E. Barth, JR.; Srivatsan Chellappa; Dean L. Lewis
- Web page: https://patentgrep.com/patent/US20150089329A1

## CPC

- G11C 29/76: {using address translation or modifications}
- G06F 8/65: Updates (security arrangements therefor G06F21/57)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 13/225: {with priority control}
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a memory under repair having variable size blocks of failed memory addresses;
a Ternary Content Addressable Memory (TCAM) comprising cells storing data values comprising ranges of addresses, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair;
a reduction circuit operatively connected to said TCAM, said reduction circuit producing a single output for each programmed range of said ranges of said addresses, based on a virtual address input to said TCAM;
a priority encoder operatively connected to said reduction circuit, said priority encoder selecting a first programmed range from said reduction circuit;
a random-access memory (RAM) operatively connected to said priority encoder, said RAM comprising cells storing data values comprising said offset value for each range of said ranges of said addresses; and
an adder having two inputs, a first input being operatively connected to said RAM and a second input being operatively connected to a virtual address line,
responsive to a virtual address being an address in one of said ranges of said addresses, said priority encoder passing said first programmed range containing said virtual address to said RAM, said RAM passing an offset value to said adder, said offset value corresponding to said first programmed range from said priority encoder, and said adder calculating a physical memory address directing said virtual address to a functional memory location in said memory under repair.

### Claim 2 (depends on 1)

The integrated circuit structure according to claim 1, said memory under repair comprising one of:
SRAM;
DRAM;
eDRAM;
MRAM;
PCM; and
Flash.

### Claim 3 (depends on 1)

The integrated circuit structure according to claim 1, contents for said TCAM and said RAM being generated separate from said integrated circuit structure.

### Claim 4 (depends on 3)

The integrated circuit structure according to claim 3, said contents of said TCAM and said RAM being programmed in at power-up of said integrated circuit structure.

### Claim 5 (depends on 1)

The integrated circuit structure according to claim 1, said ranges of said addresses being arranged in said TCAM in increasing order.

### Claim 6 (depends on 1)

The integrated circuit structure according to claim 1, said reduction circuit comprising an OR-reduction circuit.

### Claim 7 (depends on 1)

The integrated circuit structure according to claim 1, said priority encoder testing each programmed range of said ranges of said addresses and passing said first programmed range for which a next smaller range is greater-than-or-equal.

### Claim 8

A computer-implemented method, comprising:
configuring a Ternary Content Addressable Memory (TCAM) with data values comprising ranges of addresses in a memory under repair having variable size blocks of failed memory addresses, using a computerized device, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair;
receiving a virtual address, using said computerized device;
applying at least a portion of said virtual address to said TCAM, using said computerized device;
identifying a match in said TCAM indicating said virtual address being in said ranges of addresses, using said computerized device;
producing a single output for each programmed range of said ranges of said addresses, based on said virtual address, using said computerized device;
selecting a first programmed range from said ranges of addresses, using said computerized device;
passing said first programmed range to a random-access memory (RAM), using said computerized device;
outputting a corresponding offset value from said RAM as a first input to an adder, using said computerized device, said corresponding offset value corresponding to said first programmed range;
applying said virtual address as a second input to said adder, using said computerized device; and
mapping said virtual address to a physical address for a functional memory address in said memory under repair, using said computerized device.

### Claim 9 (depends on 8)

The computer-implemented method according to claim 8, said memory under repair comprising one of:
SRAM;
DRAM;
eDRAM;
MRAM;
PCM; and
Flash.

### Claim 10 (depends on 8)

The computer-implemented method according to claim 8, said configuring said TCAM with data values comprising ranges of addresses comprising generating contents for said TCAM and said RAM identifying unused functional memory locations in said memory under repair.

### Claim 11 (depends on 8)

The computer-implemented method according to claim 8, said ranges of said addresses being arranged in said TCAM in increasing order.

### Claim 12 (depends on 8)

The computer-implemented method according to claim 8, each entry in said RAM comprising an offset value for each range of said ranges of addresses in said memory under repair.

### Claim 13 (depends on 12)

The computer-implemented method according to claim 12, said mapping comprising said adder adding said offset value to said virtual address.

### Claim 14 (depends on 13)

The computer-implemented method according to claim 13, further comprising:
programming contents of said TCAM and said RAM at power-up; and
arranging said contents of said TCAM in increasing order.

### Claim 15

A system, comprising:
a memory under repair having variable size blocks of failed memory addresses;
a Ternary Content Addressable Memory (TCAM) comprising cells storing data values comprising ranges of addresses;
a reduction circuit operatively connected to said TCAM;
a priority encoder operatively connected to said reduction circuit;
a random-access memory (RAM) operatively connected to said priority encoder, said RAM comprising cells storing data values comprising an offset value for each range of said ranges of addresses; and
a processor that
identifies ranges of addresses in said memory under repair, said ranges of addresses corresponding to virtual addresses that, in combination with an offset value, point away from failed memory addresses in said memory under repair,
identifies unused functional memory locations in said memory under repair,
receives a virtual address and produces a single output for each programmed range of said ranges of addresses, using said reduction circuit,
selects a first programmed range from said reduction circuit, using said priority encoder, based on said virtual address,
calculates a physical memory address in an unused functional memory location in said memory under repair for said virtual address based on said virtual address and a corresponding offset value, said corresponding offset value corresponding to said first programmed range, and
directs said virtual address to said physical memory address in said unused functional memory location.

### Claim 16 (depends on 15)

The system according to claim 15, said memory under repair comprising one of:
SRAM;
DRAM;
eDRAM;
MRAM;
PCM; and
Flash.

### Claim 17 (depends on 15)

The system according to claim 15, contents of said TCAM and said RAM being programmed in at power-up of said system.

### Claim 18 (depends on 15)

The system according to claim 15, said ranges of addresses being arranged in said TCAM in increasing order.

### Claim 19 (depends on 15)

The system according to claim 15, said reduction circuit comprising an OR-reduction circuit.

### Claim 20 (depends on 15)

The system according to claim 15, said priority encoder testing each programmed range of said ranges of addresses and passing said first programmed range for which a next smaller range is greater-than-or-equal.