Chip testing with exclusive or

Abstract

A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel.

Dependencies are inferred from the claim text.