Event counter checkpointing and restoring
AssigneeIntel Corporation
InventorsLaura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsLaura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
Estimating the term…
Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.
A processor comprising:
A method comprising:
A non-transitory machine-readable storage medium to store instructions that, if executed, result in a processor performing operations comprising:
Dependencies are inferred from the claim text.