Checkpointing using fpga
AssigneeHewlett Packard Enterprise Development LP
InventorsKevin T. Lim, Alvin AuYoung
Life of this patent
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Abstract
Methods, systems, and computer-readable and executable instructions are provided for checkpointing using a field programmable gate array (FPGA). Checkpointing using FPGA can include checkpointing data within a region of a server's contents to memory and monitoring the checkpointed data using the FPGA.
Claims15
A computer-implemented method for checkpointing using a field programmable gate array (FPGA) comprising:
- checkpointing data within a region of a server's contents to memory;
- and
- monitoring the checkpointed data using the FPGA.
A non-transitory computer-readable medium storing a set of instructions executable by a processing resource to:
- temporarily lock a memcached hash table from access using a field-programmable gate array (FPGA);
- checkpoint a first region of a memcached server's contents to non-volatile memory while the memcached hash table is locked;
- release the lock for a period of time;
- relock the memcached hash table;
- checkpoint a second region of the memcached server's contents to the non-volatile memory while the memcached hash table is relocked;
- and
- monitor the checkpointed data within the first and second regions using the FPGA, wherein the FPGA is coherently attached to the non-volatile memory.
A system for checkpointing using a field-programmable gate array (FPGA), comprising:
- a memory resource;
- and
- a processing resource coupled to the memory resource, to:
- receive, to the FPGA, a number of address regions within a memcached server to checkpoint;
- periodically checkpoint each of the number of address regions to non-volatile memory;
- and
- automatically monitor data within each of the number of address regions using the FPGA, wherein the FPGA is coherently coupled to the non-volatile memory.
Dependencies are inferred from the claim text.