Memory controller, information processing apparatus, and method of controlling information processing apparatus
AssigneeFujitsu Limited
InventorsAkio Tokoyoda, Yuta Toyoda, Makoto Suga, Masatoshi Aihara, Koji Hosoe
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Abstract
A memory controller is provided between a CPU and a main memory, controls access from the CPU to the main memory, and includes a data storage area and a controller. In a case where error information indicating that an error occurs is included in write data from the CPU to the main memory, the controller stores the write data in a data storage area in association with a writing destination address. Therefore, even in a case where the error information is not written in the main memory, the error information can be recorded.
Claims20
A memory controller provided between a processor and a main memory and controls access from the processor to the main memory, the memory controller comprising:
- a data storage area;
- and
- a controller configured to store, when error information indicating that an error occurs is included in first write data from the processor to the main memory, the first write data in the data storage area in association with a writing destination address of the first write data.
An information processing apparatus comprising:
- a processor;
- a main memory;
- and
- a memory controller configured to be provided between the processor and the main memory and to control access from the processor to the main memory, wherein
- the memory controller includes
- a data storage area, and
- a controller configured to store, when error information indicating that an error occurs is included in first write data from the processor to the main memory, the first write data in the data storage area in association with a writing destination address of the first write data.
A method of controlling an information processing apparatus which includes a memory controller between a processor and a main memory and controls access from the processor to the main memory, the method comprising:
- receiving write data from the processor to the main memory;
- and
- storing, when error information indicating that an error occurs is included in the write data, the write data in a data storage area in the memory controller in association with a writing destination address of the write data.
Dependencies are inferred from the claim text.