System, method, and computer program product for implementing multi-cycle register file bypass
AssigneeNVIDIA Corporation
InventorsXiaogang Qiu, Ian Chi Yan Kwong, Ming Yiu Siu, Jack H. Choquette, Michael Alan Fetterman
Life of this patent
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Abstract
A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass path for each thread based on the set of control bits and the set of valid bits. Each valid bit in the set of valid bits indicates whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block.
Claims20
A method comprising:
- receiving a set of control bits;
- combining the set of control bits with a set of valid bits associated with previously issued instructions, each valid bit in the set of valid bits indicating whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block;
- and
- for each thread in the thread block, enabling or disabling one or more bypass paths based on the set of control bits and the set of valid bits.
A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:
- receiving a set of control bits;
- combining the set of control bits with a set of valid bits associated with previously issued instructions, each valid bit in the set of valid bits indicating whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block;
- and
- for each thread in the thread block, enabling or disabling one or more bypass paths based on the set of control bits and the set of valid bits.
A system comprising:
- a register file divided into a plurality of lanes, each lane including one or more bypass paths:
- a scheduler unit configured to generate a set of control bits associated with a current instruction;
- and
- a plurality of execution pipelines, wherein each execution pipeline of the plurality of execution pipelines is associated with a lane of the plurality of lanes, and wherein each lane includes logic configured to:
- receive a set of control bits,
- combine the set of control bits with a set of valid bits associated with previously issued instructions, each valid bit in the set of valid bits indicating whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block, and
- enable or disable the one or more bypass paths based on the set of control bits and the set of valid bits.
Dependencies are inferred from the claim text.