Rotate instructions that complete execution either without writing or reading flags

A multi-core processor comprising:

• at least four cores, wherein each of the at least four cores comprises:
• at least one level 1 (L1) cache;
• a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
• at least sixteen 64-bit general-purpose registers, wherein the 64-bit general-purpose registers are operable to store 64-bit operands in a 64-bit mode and are operable to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64-bit general-purpose registers;
• a branch prediction logic;
• an instruction fetch logic to fetch a rotate right instruction;
• a decoder to decode the rotate right instruction, wherein the rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and a 64-bit general-purpose register;
• a register renaming logic to rename the 64-bit general-purpose registers;
• a re-order buffer;
• and
• a plurality of execution units, including a first execution unit to execute the rotate right instruction, wherein the rotate right instruction is to rotate the first 64-bit source operand right by an amount indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand, wherein a result is to be stored into the 64-bit general-purpose register, and wherein the rotate right instruction is to complete without writing the carry flag, without writing the sign flag, without writing the zero flag, and without writing the overflow flag.

A multi-core processor comprising:

• at least four cores, wherein each of the at least four cores comprises:
• at least one level 1 (L1) cache;
• a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
• at least sixteen 64-bit general-purpose registers, wherein the 64-bit general-purpose registers are operable to store 64-bit operands in a 64-bit mode and are operable to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64-bit general-purpose registers;
• a branch prediction logic;
• an instruction fetch logic to fetch a rotate right instruction;
• a decoder to decode the rotate right instruction, wherein the rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and a 64-bit general-purpose register;
• a register renaming logic to rename the 64-bit general-purpose registers;
• a re-order buffer;
• and
• a plurality of execution units, including a first execution unit to execute the rotate right instruction, wherein the rotate right instruction is to rotate the first 64-bit source operand right by an amount indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand, wherein a result is to be stored into the 64-bit general-purpose register, and wherein the rotate right instruction is to complete without reading the carry flag, without reading the sign flag, without reading the zero flag, and without reading the overflow flag.