Predicate Vector Pack and Unpack Instructions
AssigneeApple Inc.
InventorJeffry E. Gonion
Life of this patent
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AssigneeApple Inc.
InventorJeffry E. Gonion
Estimating the term…
In an embodiment, a processor may implement a vector instruction set including predicate vectors and multiple vector element sizes. The vector instruction set may include predicate vector pack and unpack instructions. Responsive to the predicate vector pack instruction, the processor may pack predicates from multiple predicate vector source registers into a destination predicate vector register. Responsive to the predicate vector unpack instruction, the processor may select a portion of a source predicate vector register and write the result to a destination predicate vector register. Additionally, the predicate vector register may store one or more vector attributes associated with the corresponding vector. The processor may modify the attribute as part of the pack/unpack operation (e.g. based on a pack/unpack factor). Additionally, vector pack/unpack instructions that are controlled by the attribute in a corresponding predicate vector register may be implemented.
A processor comprising:
A method comprising a processor executing a first instruction defined in an instruction set architecture implemented by the processor, wherein the executing comprises:
A processor comprising:
Dependencies are inferred from the claim text.