Store address prediction for memory disambiguation in a processing device

A method, comprising:

• predicting, by a store address predictor of a processing device, an address for store operations that stores data to a memory hierarchy;
• allocating an entry in a store buffer for buffering the store operations prior to completion, the entry in the store buffer comprising the predicted address for each of the store operations;
• and
• referencing, by a load operation of the processing device, the predicted address in the store buffer to determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.

A system comprising:

• a memory hierarchy;
• and
• a processing device communicably coupled to the memory hierarchy, the processing device comprising an execution unit comprising:
• a store address predictor to predict an address for store operations that store data to the memory hierarchy;
• a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations;
• and
• a load buffer communicably coupled to the store address predictor, the load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.