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AssigneeRambus Inc.
InventorsFrederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
Estimating the term…
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
1-43. (canceled)
A memory controller adapted for use in a memory system in which the memory controller is to issue commands, each command to an addressed one of a first rank of memory or a second rank of memory, over a command/address bus having (i) at least one shared link that couples the memory controller with both of the first rank of memory and the second rank of memory in a point-to-multi-point configuration, (ii) one or more first dedicated links that couples the memory controller with the first rank of memory but not the second rank of memory, and (iii) one or more second dedicated links that couple the memory controller with the second rank of memory but not the first rank of memory, where each rank of memory has an open loop clock distribution architecture that defines a respective sampling instant used to sample each shared link of the command/address bus, and the respective first or second dedicated links, the memory controller comprising:
52-57. (canceled)
A method of accessing memory in a system having a first rank of memory and a second rank of memory, using a command/address bus having at least one shared link that couples a memory controller with both of the first rank of memory and the second rank of memory in a point-to-multi-point configuration, where each rank of memory has an open loop clock distribution architecture that defines a respective sampling instant used to sample a link of the command/address bus, the method comprising:
60-64. (canceled)
A non-transitory machine readable medium that stores data representative of an integrated circuit memory controller adapted for use in a memory system in which the memory controller is to issue commands, each command to an addressed one of a first rank of memory or a second rank of memory, over a command/address bus having (i) at least one shared link that couples the memory controller with both of the first rank of memory and the second rank of memory in a point-to-multi-point configuration, (ii) one or more first dedicated links that couples the memory controller with the first rank of memory but not the second rank of memory, and (iii) one or more second dedicated links that couple the memory controller with the second rank of memory but not the first rank of memory, where each rank of memory has an open loop clock distribution architecture that defines a respective sampling instant used to sample each shared link of the command/address bus, and the respective first or second dedicated links, the memory controller having:
Dependencies are inferred from the claim text.