Multi-granular cache management in multi-processor computing environments

A computer system for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising:
• identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;
• and
• creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.

A computer program product for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer program product comprising:

• a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising:
• identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;
• and
• creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.