Identifying high-conflict cache lines in transactional memory computing environments

A computer system for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, each cache line associated with a high-conflict indicator, the computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising:
• examining a first high-conflict indicator associated with a first cache line;
• based on the examining, placing the first cache line in a sub-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;
• executing a transaction in the computing environment, the transaction accessing a memory address within the first cache line;
• and
• accessing and managing, while executing the transaction, only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode, the relevant sub-cache line portion associated with the memory address.

A computer program product for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, each cache line associated with a high-conflict indicator, the computer program product comprising:

• a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising:
• examining a first high-conflict indicator associated with a first cache line;
• based on the examining, placing the first cache line in a sub-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;
• executing a transaction in the computing environment, the transaction accessing a memory address within the first cache line;
• and
• accessing and managing, while executing the transaction, only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode, the relevant sub-cache line portion associated with the memory address.