US 2015/0089151 A1Published application

Surface resource view hash for coherent cache operations in texture processing hardware

AssigneeNVIDIA Corporation

InventorsJeffrey Bolz, Patrick R. BROWN, Steven J. HEINRICH, Dale L. KIRKLAND, Joel MCCORMACK

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Abstract

Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

Claims20

Dependent claims

A method for performing memory access operations, the method comprising:

receiving a first memory access operation that includes a first tuple associated with a first view in a plurality of views;
retrieving a first hash value associated with a first texture header in a plurality of texture headers, wherein the first texture header is related to the first view;
retrieving a second hash value associated with a second texture header in the plurality of texture headers, wherein the second texture header is related to a second view in the plurality of views;
determining whether at least a portion of the first view is potentially aliased with at least a portion of the second view, based on the first hash value and the second hash value;
if at least a portion of the first view is potentially aliased with at least a portion of the second view, then invalidating a first cache entry in a cache memory associated with the second texture header, or
if no portion of the first view is potentially aliased with any portion of the second view, then maintaining the first cache entry associated with the second texture header.

3 more elements

A subsystem comprising:

a texture unit configured to:
receive a first memory access operation that includes a first tuple associated with a first view in a plurality of views;
retrieve a first hash value associated with a first texture header in a plurality of texture headers, wherein the first texture header is related to the first view;
retrieve a second hash value associated with a second texture header in the plurality of texture headers, wherein the second texture header is related to a second view in the plurality of views;
determine whether at least a portion of the first view is potentially aliased with at least a portion of the second view, based on the first hash value and the second hash value;
if at least a portion of the first view is potentially aliased with at least a portion of the second view, then invalidate a first cache entry in a cache memory associated with the second texture header, or
if no portion of the first view is potentially aliased with any portion of the second view, then maintain the first cache entry associated with the second texture header.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/037,212Filed 25 Sep 2013
Published: 26 Mar 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0815
Multiuser, multiprocessor or multiprocessing cache systems: cache consistency protocols
G06F 12/1018
Using page tables, e.g. page table structures: involving hashing techniques, e.g. inverted page tables
G06F 12/128
Using replacement algorithms: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 2212/455
Caching of specific data in cache memory: image or video data