Arithmetic processing device and control method for arithmetic processing device
AssigneeFujitsu Limited
InventorShigeru Kimura
Life of this patent
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Abstract
An arithmetic processing device includes: a cache memory configured to store data in a plurality of cache lines; a hardware prefetch circuit configured to prefetch data to a cache line subsequent to a cache line in which cache misses occur when the cache misses occur in cache lines whose number is p at successive addresses in the cache memory; and a controller configured to change values whose number is p in the hardware prefetch circuit when a number-of-cache-misses specifying instruction is input.
Claims5
An arithmetic processing device, comprising:
- a cache memory configured to store data in a plurality of cache lines;
- a hardware prefetch circuit configured to prefetch data to a cache line subsequent to a cache line in which cache misses occur when the cache misses occur in cache lines whose number is p at successive addresses in the cache memory;
- and
- a controller configured to change values whose number is p in the hardware prefetch circuit when a number-of-cache-misses specifying instruction is input.
A control method for an arithmetic processing device including a cache memory configured to be able to store data in a plurality of cache lines, and a hardware prefetch circuit configured to prefetch data to a cache line subsequent to a cache line in which cache misses occur when the cache misses occur in cache lines whose number is p at successive addresses in the cache memory, the control method comprising:
- causing data to be written into one cache line or the plural cache lines when a controller inputs an instruction for referencing a main memory.
Dependencies are inferred from the claim text.