US 2015/0089148 A1Published application

Memory management unit

AssigneeArm Limited

InventorsErik PERSSON, Ola HUGOSSON, Andreas BJORKLUND

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Abstract

A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Claims20

Dependent claims

A data processing apparatus comprising:

a memory management unit configured to receive one or more memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory, said memory management unit having an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored, said memory management unit being configured to select a selected entry of said internal storage unit in dependence on said virtual address,
said memory management unit further comprising an index generation unit configured to generate an index into said internal storage unit to select said selected entry in dependence on said virtual address and an identifier of said requesting master device,
wherein said index generation unit is configured to generate said index into said internal storage unit using a hash function and to generate the same index for a plurality of different inputs, and
wherein said index generation unit is configured to generate said index such that said hash function uses a different number of bits of said virtual address depending on said requesting master device.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 14/560,464Filed 4 Dec 2014
Priority: 8 Oct 2009
Published: 26 Mar 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/1018
Using page tables, e.g. page table structures: involving hashing techniques, e.g. inverted page tables
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/122
Using replacement algorithms: of the least frequently used [LFU] type, e.g. with individual count value
G06F
Computing and data processing

Family

Application12/588,263Continuation · filed 8 Oct 2009
Application14/560,464Continuation
US 2011/0087858 A1Published application
US 8,924,686 B2Related patent
US 9,213,650 B2Related patent
US 2015/0089148 A1This patent

From the US filing history. Foreign family members aren’t listed.