Maintenance Of Cache And Tags In A Translation Lookaside Buffer

A method of caching address translations in a memory architecture, comprising:

• storing translations between a first address domain and a second address domain to a first logical portion of a first cache;
• storing translations between the second addressing domain and a third address domain to a second logical portion of the first cache;
• storing translations between the first address domain and the third address domain, based on entries in the first cache, to a second cache;
• and
• storing tags associated with the translations of the first and second cache;
• detecting a deleted entry in at least one of the first logical portion and the second logical portion;
• and
• invalidating corresponding entries in the second and third caches.

A circuit comprising:

• a translation lookaside buffer (TLB) configured to store translations between address domains, the TLB addressable as a guest TLB and a root TLB, the guest TLB configured to store translations between a guest virtual address (GVA) domain and a guest physical address (GPA) domain, the root TLB configured to store translations between the GPA domain and a root physical address (RPA) domain;
• a collapsed TLB configured to store translations between the GVA domain and the RPA domain based on entries in the TLB;
• a data cache configured to store tags associated with the translations of the first and second cache;
• and
• a processor configured to detect a deleted entry in the guest TLB and invalidate corresponding entries in the collapsed TLB and data cache.