Multiple core processing with high throughput atomic memory operations

A method of operating a processor comprising multiple processor cores, wherein the processor comprises a bus for exchanging data between the multiple processor cores, wherein each of the multiple processor cores comprises at least one processor register, each of the multiple processor cores further comprises a cache for storing at least one cache line of memory, each of the multiple processor cores further comprises a load store unit for executing a memory command to exchange data between the cache and the at least one processor register, each of the multiple processor cores further comprises an atomic memory operation unit for executing an atomic memory operation on the at least one cache line of memory, each of the multiple processor cores further comprises a high throughput register for storing a status that indicates a high throughput status or a normal status, the load store unit is further operable to transfer the atomic memory operation to the atomic memory operation unit of a designated processor core selected from the multiple processor cores in the event the atomic memory operation status is the high throughput status, the load store unit is further operable to transfer the atomic memory operation to the designated atomic memory operation unit using the bus, wherein the method comprises:

• setting the status to the high throughput status on one or more of the multiple processor cores;
• issuing one or more atomic memory operations that operates on a memory address on the one or more of the multiple processor cores;
• and
• executing the one or more atomic memory operations using each of the one or more of the multiple processor cores.