Method and Apparatus for Saving Power by Efficiently Disabling Ways for a Set-Associative Cache
AssigneeIntel Corporation
InventorsMartin Licht, Jonathan Combs, Andrew Huang
Life of this patent
Estimating the term…
Abstract
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.
Claims4
A method comprising:
- counting, in a counter, a number of cache misses to each way, respectively, of a plurality of ways of a cache memory set;
- generating a power signal, associated with any first way of the plurality of ways of the cache memory set, to power down the first way, if the counted number of misses to the first way in the respective counter reaches a saturation value.
Dependencies are inferred from the claim text.