Microprocessor with integrated nop slide detector
AssigneeVIA Technologies, Inc.
InventorTerry Parks
Life of this patent
Estimating the term…
Abstract
A microprocessor includes an instruction cache and a hardware state machine configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero. The microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions.
Claims21
A microprocessor, comprising:
- an instruction cache;
- a hardware state machine, configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero;
- and
- wherein the microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions.
A method performed by a microprocessor having an instruction cache and a hardware state machine, the method comprising:
- detecting, by the hardware state machine, a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero;
- and
- suspending fetching and executing instructions from the instruction cache in response to said detecting the continuous sequence of N NOP instructions.
A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
- computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising:
- first program code for specifying an instruction cache;
- and
- second program code for specifying a hardware state machine, configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero;
- and
- wherein the microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions.
Dependencies are inferred from the claim text.