Microprocessor and method for using an instruction loop cache thereof

A method for using an instruction loop cache, comprising:

• entering a normal state initially, wherein the instruction loop cache is associated with a finite state machine that includes the normal state and an inner state;
• updating the instruction loop cache with a tag value sent from a processor core to the instruction loop cache when a current state is the normal state and the tag value is different from every tag value previously stored in the instruction loop cache;
• entering the normal state when the current state is the inner state and the tag value sent from the processor core to the instruction loop cache is different from every tag value previously stored in the instruction loop cache;
• entering the inner state when the current state is the normal state in response to receiving an inner signal;
• and
• determining whether the cache hit or a cache miss occurs in the instruction loop cache based on a comparison between a tag of a fetch address sent from the processor core to the instruction loop cache and one of the tag values stored in the instruction loop cache.