Data Compression In Processor Caches

A system comprising:

• a processor comprising:
• at least one core to execute instructions;
• a plurality of physical ways, each physical way including a first portion and a second portion, the first portion to store one of a plurality of baseline ways, the second portion to store one of a plurality of victim ways, the plurality of baseline ways forming a baseline cache, the plurality of victim ways forming a victim cache;
• cache logic to:
• select a first victim way based on a size of an associated baseline way;
• evict a first data element from a first baseline way to the first victim way;
• and
• a dynamic random access memory (DRAM) coupled to the processor.

A method, comprising:

• receiving, by a cache control logic, a request for a first data element;
• determining, by the cache control logic, whether the first data element is stored in one of a plurality of baseline ways, wherein each one of the plurality of baseline ways is stored, along with a corresponding one of a plurality of victim ways, in one of a plurality of physical ways of a cache memory;
• in response to a determination that the first data element is not stored in one of the plurality of baseline ways:
• evicting a first baseline way of the plurality of baseline ways;
• obtaining the first data element;
• and
• storing the first data element in the first baseline way.