Accessing data stored in a command/address register device
AssigneeIntel Corporation
InventorsKuljit S. Bains, Klaus J. Ruff, George Vergis, Suneeta Sah
Life of this patent
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Abstract
A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
Claims20
An apparatus comprising:
- a dynamic random access memory (DRAM) comprising at least one page having at least one multipurpose register (MPR) and comprising:
- a first interface that, when operatively coupled to an address bus, is to receive a control word (CW) and provide the CW to a particular MPR and
- a second interface communicatively coupled to the at least one page having at least one MPR, wherein:
- the at least one page having at least one MPR to be written-to using the first interface during a coupling of the first interface to the address bus and to be read-from using the second interface during a coupling of the second interface to the data bus.
A computer-implemented method comprising:
- receiving, at a multipurpose register (MPR), a control word (CW) from an address bus interface, wherein the MPR is associated with a dynamic random access memory (DRAM) and
- transmitting content from the MPR using a data bus interface.
An apparatus to write a control word (CW), the apparatus comprising:
- a register;
- a memory controller to provide a command, the command to cause the register to write a CW to at least one multipurpose register (MPR) associated with a dynamic random access memory (DRAM);
- and
- an address bus interface communicatively coupled to the register, the address bus interface to provide the CW for transfer to an MPR associated with the command.
Dependencies are inferred from the claim text.