Clock signals for dynamic reconfiguration of communication link bundles
AssigneeHewlett-Packard Development Company, L.P.
InventorsRobert Wessel, Peter David Maroni
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Abstract
In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.
Claims15
An electronic device, comprising:
- a plurality of communication link bundles that provide communication between a processor of the electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes;
- and
- a plurality of clock selection circuits, one for each communication link bundle, each one dynamically selecting a clock signal out of multiple clock signals for use by its respective communication link bundle.
A serial communication link controller of an electronic device, comprising:
- a plurality of communication link bundles that provide communication between a processor of the electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes;
- and
- a plurality of clock selection circuits, at leash one for each communication link bundle, each one dynamically selecting a clock signal out of multiple clock signals for use by at least part of its respective communication link bundle.
A method, comprising:
- providing a plurality of communication link bundles that allow for communication between a processor of an electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes;
- generating multiple clock signals based on an input clock;
- dynamically selecting, by each of a plurality of clock selection circuits, a clock signal out of multiple clock signals, wherein each clock selection circuit is associated with one of the communication link bundles;
- and
- using, by each communication link bundle, the clock signal selected for the particular communication link bundle.
Dependencies are inferred from the claim text.