Providing A Serial Protocol For A Bidirectional Serial Interconnect
AssigneeIntel Corporation
InventorsDavid J. Harriman, Jeff C. Morriss
Life of this patent
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Abstract
In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a transmit logic including:
- transaction logic and link logic to prepare data into a packet, the packet including a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value;
- and
- a physical unit (PHY) to transmit the packet to at least one device via an interconnect, the PHY including a first driver to send the packet and a second driver to send a clock signal.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving data in a transmission logic of a host controller;
- generating a content portion of a packet based on the data;
- generating an error detection portion of the packet based on the content portion;
- forming the packet including a first start bit, a preamble portion following the first start bit, a second start bit following the preamble portion, the content portion, a third start bit following the content portion, the error detection portion, a fourth start bit following the error detection portion, and a postamble portion;
- and
- communicating the packet along an interconnect coupled to the host controller via a physical unit of the host controller.
A system comprising:
- a system on a chip (SoC) including:
- a plurality of cores;
- a transaction layer and a link layer of a Peripheral Component Interconnect Express™ (PCIe™) communication protocol;
- and
- a physical unit coupled to the link layer to enable communication via a physical link, the physical unit comprising an electrical layer not of the PCIe™ communication protocol and a logical layer;
- a second physical unit having a transmission logic to receive data and to prepare a packet for communication via a second physical link, the packet including a first start bit, a preamble portion having a first value, a second start bit having a different value than the first start bit, a content portion including the data represented by a plurality of symbols, a third start bit, an error detection portion including an inverted version of the content portion, a fourth start bit, and a postamble portion having a second value;
- the physical link coupled between the SoC and a device;
- the second physical link coupled between the SoC and at least one sensor device;
- the device coupled to the SoC via the physical link;
- and
- the at least one sensor device coupled to the SoC via the second physical link.
Dependencies are inferred from the claim text.