Microelectronic interconnect element with decreased conductor spacing
AssigneeInvensas Corporation
InventorsChang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
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Abstract
A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.
Claims9
A method of forming a microelectronic interconnect element, comprising:
- (a) given a layered element including a first thin exposed metal layer having a first thickness, a second exposed metal layer having a second thickness substantially greater than the first thickness, and a removable layer sandwiched between the first and second metal layers, plating a plurality of first metal lines onto a first surface of the first metal layer;
- (b) forming a dielectric layer overlying the first metal lines;
- (c) removing at least the second metal layer and the removable layer to expose a second surface of the first metal layer;
- (d) plating a plurality of second metal lines onto the second surface of the first metal layer;
- and
- (e) removing at least a portion of the first metal layer exposed between the first and second metal lines.
Dependencies are inferred from the claim text.