Jog Design in Integrated Circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
Life of this patent
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Abstract
A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
Claims20
A method comprising:
- forming a gate strip of a Metal-Oxide-Semiconductor (MOS) device over an active region, wherein the gate strip comprises a strip portion and a jog;
- forming a first Inter-Layer Dielectric (ILD), with the gate strip being in the first ILD;
- forming a first contact plug in the first ILD and connected to a source/drain region of the MOS device;
- forming a second ILD over the first ILD;
- forming first opening in the second ILD, wherein a portion of the first contact plug is directly underlying and exposed to a first portion of the first opening, and a portion of the first ILD is directly underlying and exposed to a second portion of the first opening;
- forming a second opening connected to the first opening to form a continuous opening, wherein a portion of the jog is directly underlying and exposed to the second opening;
- and
- filling the continuous opening to form a second contact plug.
A method comprising:
- forming a gate strip of a Metal-Oxide-Semiconductor (MOS) device over an active region, wherein the gate strip comprises a strip portion and a jog;
- forming a first Inter-Layer Dielectric (ILD), with the gate strip being in the first ILD;
- forming a first contact plug in the first ILD and overlapping a source/drain region of the MOS device;
- forming a second ILD over the first ILD;
- in a first etching step, etching the second ILD to form a first opening in the second ILD, wherein a portion of the first contact plug is directly underlying and exposed to a portion of the first opening;
- in a second etching step, etching the second ILD to form a second opening, wherein a portion of the jog is directly underlying and is exposed to the second opening;
- and
- filling the first opening and the second opening to form a second contact plug.
A method comprising:
- forming a gate strip of a Metal-Oxide-Semiconductor (MOS) device;
- forming a first Inter-Layer Dielectric (ILD), with the gate strip being in the first ILD;
- forming a first contact plug in the first ILD and connected to a source/drain region of the MOS device, with a top surface of the first contact plug being substantially level with a top surface of the gate strip;
- forming a second ILD over the first ILD;
- etching the second ILD to form a continuous opening comprising:
- a first portion directly over a portion of the first ILD;
- a second portion overlapping the first contact plug, with a top surface of the first contact plug exposed to the second portion of the continuous opening;
- and
- a third portion overlapping the gate strip, with a top surface of the gate strip exposed to the third portion of the continuous opening;
- and
- filling the continuous opening with a conductive material to form a second contact plug.
Dependencies are inferred from the claim text.