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US 2015/0087135 A1Published application
Method of forming a trench isolation structure using a sion layer
AssigneeTexas Instruments Incorporated
InventorsYaojian Leng, Scott Allyn Kolda
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Abstract
A moat, which is a region of a semiconductor wafer that is laterally surrounded by a trench isolation structure, is protected from damage due to dishing or low spots that result from chemical-mechanical polishing by forming a patterned hard mask structure with an upper silicon oxynitride layer, and performing the polishing with a slurry that includes ceria.
Claims15
A method of forming a trench isolation structure comprising:
- forming a patterned hard mask structure on a top surface of a semiconductor wafer, the patterned hard mask structure having a silicon oxynitride layer, and an opening that exposes a region on the top surface of the semiconductor wafer;
- etching the semiconductor wafer through the opening in the patterned hard mask structure to form a trench in the semiconductor wafer;
- lining the trench with a non-conductive material to form a lined trench;
- filling the lined trench with a semiconductor material, the semiconductor material touching the non-conductive material and lying over the patterned hard mask structure;
- and
- chemically-mechanically polishing the semiconductor material.
3 more elements
A method of forming a trench isolation structure comprising:
- forming a pad oxide layer on a top surface of a semiconductor wafer;
- forming a silicon nitride layer on the pad oxide layer;
- forming a silicon oxynitride layer on the silicon nitride layer;
- forming an opening that extends through the silicon oxynitride layer, the silicon nitride layer, and the pad oxide layer to expose the top surface of the semiconductor wafer;
- and
- etching the semiconductor wafer through the opening to form a trench in the semiconductor wafer.
3 more elements
Dependencies are inferred from the claim text.