Mosfet with source side only stress
AssigneeTexas Instruments Incorporated
InventorsSamuel Zafar Nawaz, Shaofeng YU, Jeffrey E. BRIGHTON, Song ZHAO
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Abstract
An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.
Claims9
A method of forming an integrated circuit having a transistor with stress enhancement on a source side only, comprising;
- providing a semiconductor substrate having a gate formed thereon;
- forming a masking layer that exposes a first portion of said substrate on a source side of said gate and masks a second portion of said substrate on a drain side of said gate;
- etching a recess into said substrate on said source side of said gate;
- epitaxially growing a stress enhancement layer to refill said recess on said source side of said gate;
- and
- removing said masking layer.
A method of forming an integrated circuit having a transistor with stress enhancement on a source side only, comprising;
- providing a semiconductor substrate having a gate formed thereon;
- forming a pattern on said semiconductor substrate opening a source region adjacent to said gate;
- implanting said source region with a stress enhancing species;
- and
- annealing said implant.
Dependencies are inferred from the claim text.