Cmos structures and methods for improving yield
AssigneeInternational Business Machines Corporation
InventorsHuilong Zhu, Daewon Yang
Life of this patent
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Abstract
A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
Claims17
A method of forming a semiconductor structure comprising:
- forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate;
- forming at least one stressed layer having a stress located over the first transistor and the second transistor, said at least one stressed layer having a deposited thickness over the first and second transistors;
- and
- sputter etching said at least one stressed layer to provide at least one etched stressed layer that has an etched thickness over the first and second transistors that is less than said deposited thickness, wherein said at least one etched stressed layer over each of said first and second transistors has tapered surface sidewalls that meet each other.
A method of forming a semiconductor structure comprising:
- forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate, wherein at least one dummy gate is located on a surface of an isolation region in said substrate between said first and second transistors;
- forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the first stressed layer and the second transistor, said second stressed layer having a deposited thickness over the second transistor, where the first stressed layer and the second stressed layer abut and overlap each other in an area between the first and second transistors defining an overlap area having an overlap thickness;
- and
- selectively sputter etching said second stressed layer to provide an etched stressed layer having an etched thickness that is less than said deposited thickness over the second transistor and said etched second stressed layer over said second transistor has tapered surface sidewalls that meet each other, and wherein said overlap thickness has been reduced and said etched second stressed layer in said overlap area has tapered surface sidewalls that meet each other.
Dependencies are inferred from the claim text.