US 2015/0087120 A1 · Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer

Abstract

A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer.

Claims20

Dependent claims

A method of forming a semiconductor device, the method comprising:

forming a gate portion on a surface of a semiconductor substrate, the gate portion having gate sidewalls;
forming gate spacers on the gate sidewalls and on the surface of the semiconductor substrate, the gate spacers having first sidewalls;
forming raised source/drain (RSD) regions on the surface of the semiconductor substrate, the RSD regions having a faceted side portion contacting the gate spacers at the surface of the semiconductor substrate, thereby forming cavity regions defined by the gate sidewalls and the faceted side portion of the RSD regions;
filling the cavity regions with a dielectric material, thereby forming dielectric regions;
and
forming second spacers on the first sidewalls and on a top surface of the dielectric regions, the second spacers having second sidewalls.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/556,638Filed 1 Dec 2014

Priority

2 May 2013

Published

26 Mar 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/259
Characterised by the relative positions of the source or drain electrodes with respect to the gate electrode: source or drain electrodes being…
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes

Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer

Life of this patent

Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer

Life of this patent

Abstract

Claims20