Compact, low power advanced encryption standard circuit
AssigneeIntel Corporation
InventorsSanu MATHEW, Vikram Suresh, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Ram Krishnamurthy
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Abstract
Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
Claims21
An apparatus comprising:
- an encryption unit to perform encryption according to an Advanced Encryption Standard algorithm, the encryption unit including a substitution box to perform a substitution operation on one byte per clock cycle and an accumulator to accumulate four bytes and perform a mix-column operation in four clock cycles.
A method comprising:
- accumulating four accumulator input bytes in four clock cycles to perform a mix-column operation of an Advanced Encryption Standard algorithm.
A system comprising:
- a processor including
- an encryption unit to generate cipher-text from plain-text according to an Advanced Encryption Standard algorithm, the encryption unit including a substitution box to perform a substitution operation on one byte per clock cycle and an accumulator to accumulate four bytes and perform a mix-column operation in four clock cycles;
- and
- a memory to store the cipher-text.
A method comprising:
- developing a hardware description language model of an encryption unit, the encryption unit to perform an Advanced Encryption Standard algorithm and including an eight-bit datapath having a single substitution box to perform a substitution operation on one byte per clock cycle;
- developing a plurality of parameter files, each parameter file for one of a plurality of a plurality of polynomial pairs for Galois field mapping;
- simulating the operation of the encryption unit using the plurality of parameter files to determine the optimum polynomial pair for minimum area of the encryption unit meeting timing and design rule constraints.
Dependencies are inferred from the claim text.