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US 2015/0085873 A1Published application
Header replication in accelerated tcp (transport control protocol) stack processing
AssigneeIntel Corporation
InventorsLinden Cornett, David B. Minturn, Sujoy Sen, Hemal V. Shah, Anshuman Thakur, Gary Tsao, Anil Vasudevan
Life of this patent
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Abstract
In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.
Claims17
A method comprising:
- performing packet processing on a plurality of packets including extracting payloads from said plurality of packets;
- using a direct memory access (DMA) operation of a data movement circuit to place the payloads corresponding to said plurality of packets into a read buffer substantially simultaneously while performing packet processing.
An apparatus comprising:
- circuitry to:
- perform packet processing on a plurality of packets including extracting payloads from said plurality of packets;
- and
- substantially simultaneously with the circuitry to perform packet processing, the circuitry to use a direct memory access (DMA) operation of a data movement circuit to place said payload corresponding to said plurality of packets into a read buffer.
1 more element
A system comprising:
- a chipset having a DMA (direct memory access) engine, the chipset communicatively coupled to a transport protocol driver of a processor and to a network component;
- and circuitry to:
- perform packet processing on a plurality of packets including extracting payloads from said plurality of packets;
- and
- substantially simultaneously with the circuitry to perform packet processing, the circuitry to use a direct memory access (DMA) operation of the DMA engine to place said payloads corresponding to said plurality of packets into a read buffer.
2 more elements
A non-transitory machine readable storage medium which stores instructions executable by a machine which performs the following:
- performing packet processing on a plurality of packets including extracting payloads from said plurality of packets;
- and
- causing a direct memory access (DMA) operation of a data movement circuit to place said payloads corresponding to said plurality of packets into a read buffer substantially simultaneously while performing packet processing.
Dependencies are inferred from the claim text.