Protocol For Refresh Between A Memory Controller And A Memory Device

A method of controlling a dynamic random access memory device (DRAM) by a memory controller integrated circuit, the method comprising:

• outputting a first memory command to the DRAM via a first communications link, wherein the first command is used to initiate a refresh operation to a first bank of the DRAM;
• and
• outputting a second memory command to the DRAM via a second communications link, wherein the second command is used to initiate a memory operation to a second bank of the DRAM while the refresh operation is being executed in the first bank;
• wherein the memory operation is to be performed concurrent with performance of the refresh operation in the first bank.

A memory controller integrated circuit to control a dynamic random access memory device (DRAM) having first and second sets of banks, each bank containing an array of DRAM memory cells, the memory controller integrated circuit comprising:

• a first interface to output a first memory command to the DRAM via a first communications link;
• a second interface to output a second memory command to the DRAM via a second communications link;
• first controller logic, coupled to the first interface, to control memory operations in the second set of banks, the first controller logic to generate the first command, wherein the first command initiates a self-refresh operation to a first bank of the first set of banks, the self-refresh operation to be performed during a time interval;
• and
• second controller logic, coupled to the second interface, to control memory operations in the second set of banks, the second controller logic to generate the second command, wherein the second command initiates a memory operation to a first bank of the second set of banks to initiate a second refresh operation in the DRAM via the second interface during the time interval.