Bit-Line Discharge Assistance in Memory Devices
AssigneeLSI Corporation
InventorsDharmendra Kumar Rai, Rahul Sahu
Life of this patent
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Abstract
One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.
Claims10
An apparatus comprising:
- a memory array of memory cells arranged in at least one column that is coupled to a read bit line;
- a discharge device coupled to the read bit line and configured to provide discharge assistance to the read bit line;
- and
- a discharge assistance controller coupled to the discharge device and configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.
A method for operating an apparatus comprising a memory array of memory cells arranged in at least one column that is coupled to a read bit line, wherein the method comprises:
- (a) providing discharge assistance to the read bit line;
- and
- (b) modifying duration of the discharge assistance in correlation with capacitance of the read bit line.
Dependencies are inferred from the claim text.