Ping-pong buffer using single-port memory

Abstract

A method of controlling a ping-pong buffer includes selectively providing one of a ping gated write clock signal and a ping gated read clock signal to a single-port ping buffer, and selectively providing a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A controller of a ping-pong buffer includes a ping multiplexer and a pong multiplexer. The ping multiplexer selectively provides a ping gated write clock signal or a ping gated read clock signal to a single-port ping buffer. The pong multiplexer selectively provides a pong gated write clock signal or a pong gated read clock signal to a single-port pong buffer. A ping-pong buffer system includes a ping buffer, a pong buffer, a ping multiplexer, and a pong multiplexer. The ping buffer and pong buffer each include a single-port memory.

Dependencies are inferred from the claim text.