Memory device and method of operation of such a memory device

A method of operating a memory device to perform a write operation, the memory device comprising an array of memory cells connected to a core voltage level and arranged as a plurality of rows and columns, each row being connected to an associated word line, and each column being connected to an associated at least one bit line, the columns being arranged into a plurality of column groups, each column group containing a plurality of columns, the method comprising:

• employing access circuitry to perform the write operation in order to write data into a plurality of addressed memory cells, said plurality of addressed memory cells comprising an addressed memory cell within each of a plurality of the column groups, the access circuitry receiving both the core voltage level and a peripheral voltage level less than said core voltage level;
• precharging, to said peripheral voltage level, the at least one bit line associated with at least each column containing an addressed memory cell, prior to said write operation being performed;
• during the write operation causing the access circuitry to:
• assert a word line signal at the core voltage level on the word line associated with a row of the array containing the plurality of addressed memory cells;
• employ write driver circuitry to control the voltage on the at least one bit line of each of the addressed memory cells in order to store write data into the plurality of addressed memory cells;
• couple the at least one bit line of each addressed memory cell to the write driver circuitry, in dependence on a mux control signal identifying which column in each of said plurality of column groups contains the addressed memory cells;
• and
• assert said mux control signal to the write multiplexing circuitry at said core voltage level.

A memory device comprising:

• an array of memory cell means connected to a core voltage level and arranged as a plurality of rows and columns, each row being connected to an associated word line means, and each column being connected to an associated at least one bit line means, the columns being arranged into a plurality of column groups, each column group containing a plurality of columns;
• access means for performing a write operation in order to write data into a plurality of addressed memory cell means, said plurality of addressed memory cell means comprising an addressed memory cell means within each of a plurality of the column groups, the access means for receiving both the core voltage level and a peripheral voltage level less than said core voltage level;
• the access means comprising:
• word line driver means for asserting a word line signal at the core voltage level on the word line means associated with a row of the array containing the plurality of addressed memory cell means;
• precharge means for precharging, to said peripheral voltage level, the at least one bit line means associated with at least each column containing an addressed memory cell means, prior to said write operation being performed;
• write driver means for controlling the voltage on the at least one bit line means of each of the addressed memory cell means during the write operation in order to store write data into the plurality of addressed memory cell means;
• write multiplexing means for coupling, during the write operation, the at least one bit line means of each addressed memory cell means to the write driver means, in dependence on a mux control signal identifying which column in each of said plurality of column groups contains the addressed memory cell means;
• and
• write multiplexing driver means for asserting said mux control signal to the write multiplexing means at said core voltage level.