Nvm device using fn tunneling with parallel powered source and drain
AssigneeSynopsys, Inc.
InventorsAndrew E. Horch, Troy N. Gilliland
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.
Claims26
A non-volatile memory bitcell comprising:
- a tunneling device comprising:
- a first portion of a floating gate, and
- a first active region of a substrate beneath the first portion of the floating gate, the applying of a tunneling voltage to the first active region causing charge carriers to transition to the floating gate;
- a transistor comprising:
- a second portion of the floating gate,
- a source in a second active region of the substrate, and
- a drain in the second active region, a current flowing between the source and drain based on a voltage level of the floating gate and a voltage difference between the source and the drain;
- and
- a capacitor comprising:
- a first plate comprising a third active region of the substrate, and
- a second plate comprising a third portion of the floating gate above the third active region, the third portion of the floating gate capacitively coupling the floating gate to the third active region to control charge carrier transition in the tunneling device and the current between the source and the drain of the transistor.
A non-volatile memory device comprising:
- a plurality of non-volatile memory bitcells formed with a substrate, the bitcells arranged along a plurality of rows and a plurality of columns, each bitcell comprising:
- a tunneling device comprising a first active region of the substrate and a first portion of a floating gate extending over the first active region,
- a transistor comprising a second active region of the substrate, the second active region of the substrate comprising a source, a drain, the transistor further comprising a second portion of the floating gate extending over the second active region, and
- a capacitor comprising a third active region of the substrate and a third portion of the floating gate extending over the third active region;
- a first conductive line electrically coupling tunneling devices of a first plurality of the bitcells along one of the plurality of rows;
- a second conductive line electrically coupling capacitors of the first plurality of bitcells along the same row;
- a third conductive line electrically coupling sources of a second plurality of the bitcells along one of the plurality of columns;
- and
- a fourth metal line for electrically coupling drains of the second plurality of the bitcells along the same column.
A non-transitory machine readable medium that stores data representing a non-volatile memory bitcell that comprises:
- a tunneling device comprising:
- a first portion of a floating gate, and
- a first active region of a substrate beneath the first portion of the floating gate, the applying of a tunneling voltage to the first active region causing charge carriers to transition to the floating gate;
- a transistor comprising:
- a second portion of the floating gate,
- a source in a second active region of the substrate, and
- a drain in the second active region, a current flowing between the source and drain based on a voltage level of the floating gate and a voltage difference between the source and the drain;
- and
- a capacitor comprising:
- a first plate comprising a third active region of the substrate, and
- a second plate comprising a third portion of the floating gate above the third active region, the third portion of the floating gate capacitively coupling the floating gate to the third active region to control charge carrier transition in the tunneling device and the current between the source and the drain of the transistor.
A computer-readable tangible storage medium comprising instructions configured to be operated by a computer system to:
- perform an erase operation on a row of bitcells,
- each bitcell comprising a floating gate above a first active region forming a tunneling device, a second active region forming a transistor comprising a source and a drain, and a third active region forming a capacitor,
- the erase operation comprising instructions to:
- adjust to a tunneling voltage a first metal line coupled to the first active regions;
- perform a program operation on one of the bitcells of the row, the program operation comprising instructions to:
- adjust to the tunneling voltage the first metal line and a second metal line coupled to the third active regions,
- adjust to a moderate voltage a third metal line coupled to a plurality of sources of a plurality of bitcells along a column, one of the bitcells of the column also being a part of the row, and
- adjust to the same moderate voltage a fourth metal line coupled to a plurality of drains of the bitcells along the column;
- and
- perform a read operation on the programmed bitcell, the read operation comprising instructions to:
- adjust the second metal line to the moderate voltage;
- and
- adjust the third metal line to a voltage different from that of the fourth metal line.
Dependencies are inferred from the claim text.