Semiconductor memory device and operating method thereof
AssigneeSK hynix Inc.
InventorSung Dae CHOI
Life of this patent
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Abstract
A semiconductor memory device and an operating method thereof are provided. The semiconductor memory device includes a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells, a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells, and a control logic suitable for controlling the voltage generator to generate the pass voltage to have different levels depending on a distance between the drain-select transistor and the selected memory cell during a read operation.
Claims14
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells;
- a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells;
- and
- a control logic suitable for controlling the voltage generator to generate the pass voltage having different levels depending on a distance between the drain-select transistor and the selected memory cell during a read operation.
A method of operating a semiconductor memory device including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells, the method comprising:
- during a read operation, generating a pass voltage having different levels depending on a distance between the drain-select transistor and a selected memory cell of the memory cells;
- and
- applying the pass voltage to unselected memory cells other than the selected memory cell among the memory cells.
A semiconductor memory system comprising:
- a semiconductor memory device;
- and
- a controller suitable for controlling the semiconductor memory device,
- wherein the semiconductor memory device comprises:
- a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells;
- a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells;
- and
- a control logic suitable for controlling the voltage generator to generate the pass voltage to have different levels depending on a distance between the drain-select transistor and the selected memory cell during a read operation.
Dependencies are inferred from the claim text.