Contact structure and forming method
AssigneeMacronix International Co., Ltd.
InventorShih-Hung CHEN
Life of this patent
Estimating the term…
Abstract
Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.
Claims20
A method for forming vias within a stack of layers comprising:
- forming a stack of alternating active layers and insulating layers, comprising:
- forming a first sub stack comprising N active layers separated by insulating layers;
- forming a second sub stack over the first sub stack, the second sub stack comprising M active layers separated by insulating layers;
- and
- forming a first buffer layer between the first and second sub stacks and a second buffer layer under the first sub stack;
- exposing an upper layer of the first sub stack through a set of vias by:
- etching, using a first etching process to form a first set of etch vias through the second sub stack and stopping at or in the first buffer layer, and then
- etching, using a second etching process through the first buffer layer to the upper layer of the first sub stack;
- and
- etching through the first sub stack by:
- etching, using a third etching process through the first set of etch vias through the first sub stack and stopping at or in the second buffer layer, and then
- etching, using a fourth etching process through the second buffer layer.
A stairstep contact structure comprising:
- a stack of alternating active layers and insulating layers having non-simple spatial periods;
- the stack of alternating active layers and insulating layers comprises:
- a first sub stack comprising N active layers separated by insulating layers, the N active layers comprising an upper boundary active layer;
- a second sub stack over the first sub stack, the second sub stack comprising M active layers separated by insulating layers, the M active layers comprising an upper boundary active layer;
- and
- a first buffer layer between the first and second sub stacks, the first buffer layer having an etching time greater than the etching time of an insulating layer of the second sub stack for a given etching process;
- a stairstep structure of landing areas on the active layers;
- and
- interlayer conductors extending to the landing areas, the interlayer conductors separated from one another by insulating material.
A circuit, comprising:
- a substrate;
- and
- a NAND-connected string of transistors on the substrate, including:
- a first plurality of nonvolatile memory cells having a first gate length;
- a second plurality of nonvolatile memory cells having a second gate length greater than the first gate length,
- wherein an electrical channel through the NAND-connected string has an orientation perpendicular to the substrate.
A circuit, comprising:
- a substrate;
- a plurality of stacks of semiconductor strips on the substrate, the semiconductor strips in the plurality of stacks including at least a first semiconductor strip having a first height, and a second semiconductor strip having a second height, the first height and the second height being different;
- and
- a plurality of word lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of memory elements is established at cross-points between surfaces of the plurality of stacks and the plurality of word lines, and such that a plurality of NAND-connected strings of transistors are formed along the semiconductor strips in the plurality of stacks, including:
- a first NAND-connected string of nonvolatile memory cells having the first height;
- and
- a second NAND-connected string of nonvolatile memory cells having the second height.
Dependencies are inferred from the claim text.