Back Gate Operation with Elevated Threshold Voltage
AssigneeSanDisk Technology Inc.
InventorsDeepak Raghu, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui
Life of this patent
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Abstract
In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.
Claims18
A method of operating a block of a three dimensional nonvolatile memory array comprising:
- applying a first set of programming conditions that includes a first back gate voltage that is applied to a back gate of the block for programming operations during a first period of operation;
- performing one or more back gate tuning operations on the back gate of the block to maintain threshold voltage of a back gate transistor in a target range;
- subsequently determining that the threshold voltage of the back gate transistor remains higher than the target range after back gate tuning;
- and
- subsequently, replacing the first set of programming conditions with a second set of programming conditions that includes a second back gate voltage that is applied to the back gate of the block for programming operations during a second period of operation, the second back gate voltage being larger than the first back gate voltage.
A method of operating a block of a three dimensional nonvolatile memory array comprising:
- applying a default set of programming conditions that includes a first back gate voltage that is applied to a back gate of the block for programming cells along word lines near the back gate during a first period of operation;
- subsequently determining that the threshold voltages of the back gate transistors are higher than a target range;
- and
- subsequently, replacing the default set of programming conditions with a modified set of programming conditions that includes a second back gate voltage that is applied to the back gate of the block for programming cells along word lines near the back gate during a second period of operation, the second back gate voltage being larger than the first back gate voltage.
A three dimensional nonvolatile memory system comprising:
- a plurality of NAND strings that individually include two wings that each extend in a direction perpendicular to a surface of a substrate, the two wings connected by a back gate transistor;
- a back gate that forms a common gate terminal for all back gate transistors of a block;
- and
- a back gate control circuit that controls a voltage applied to the back gate, the back gate control circuit configured to supply a first boosting voltage to the back gate during programming in a first period of operation of the block and configured to supply a second boosting voltage to the back gate during programming in a subsequent second period of operation of the block, the second boosting voltage being higher than the first boosting voltage.
Dependencies are inferred from the claim text.