Read/write assist for memories
AssigneeQUALCOMM Incorporated
InventorsChirag GULATI, Rakesh SINHA, Ritu CHABA, Sei Seung YOON
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.
Claims45
An integrated circuit, comprising:
- one or more bit cells;
- a word line coupled to the one or more bit cells;
- a dummy word line arranged with the word line to have a capacitance therebetween;
- a base layer having a plurality of transistors;
- a first metal layer interconnecting the transistors to form the one or more bit cells;
- a second metal layer comprising the word line;
- and
- a third metal layer comprising the dummy word line;
- wherein the first metal layer is between the base layer and the second metal layer and the second metal layer is between the first and third metal layers.
4-6. (canceled)
An integrated circuit, comprising:
- one or more bit cells;
- a word line coupled to the one or more bit cells;
- dummy word line means for affecting a voltage applied to the word line through a capacitive coupling therebetween;
- a base layer having a plurality of transistors;
- a first metal layer interconnecting the transistors to form the one or more bit cells;
- a second metal layer comprising the word line;
- and
- a third metal layer comprising the dummy word line means,
- wherein the first metal layer is between the base layer and the second metal layer and the second metal layer is between the first and third metal layers.
18-20. (canceled)
A method of manufacturing an integrated circuit, comprising:
- forming a plurality of transistors and interconnecting the transistors to form one or more bit cells;
- forming a word line and interconnecting the word line to the one or more bit cells;
- and
- forming a dummy word line and arranging the dummy word line with the word line to form a capacitance therebetween,
- wherein the transistors are formed in a base layer and interconnected by a first metal layer, the word line is formed in a second metal layer, and the dummy word line is formed in a third metal layer, and wherein the first metal layer is between the base layer and the second metal layer and the second metal layer is between the first and third metal layers.
32-34. (canceled)
A method of controlling a word line coupled to one or more bit cells formed in an integrated circuit, comprising:
- asserting the word line to access the one or more bit cells;
- and
- controlling a dummy word line to affect a voltage applied to the word line, the voltage being affected by a capacitive coupling between the word line and the dummy word line,
- wherein the integrated circuit further comprises:
- a base layer having a plurality of transistors;
- a first metal layer interconnecting the transistors to form the one or more bit cells;
- a second metal layer comprising the word line;
- and
- a third metal layer comprising the dummy word line, and wherein the first metal layer is between the base layer and the second metal layer and the second metal layer is between the first and third metal layers.
45-47. (canceled)
Dependencies are inferred from the claim text.